Cascaded-Integrator-Comb (CIC) filters are ubiquitous in digital signal processing (DSP) applications where efficient interpolation and decimation of oversampled signals is required. Since their introduction the early 1980's, a plethora of research has been dedicated to the improvement of their major weakness: limited worst-case stopband attenuation caused by the fact that all zeros at each stopband null are at the same location instead of being optimally distributed.
Previous approaches have focused on a zero-rotating approach, where structural changes are incorporated to the classical filter with the aim to widen the stopbands by spreading the zeros closer to their optimal location. Another approach is based on a filter sharpening approach, where a sharpening polynomial is applied to the stopbands of the filter. The concepts of polyphase decomposition, multistage factoring and non-recursive implementation of the underlying finite impulse response (FIR) filter have also been applied to the original CIC filter.
CIC filters are simple because the structure is composed solely of integrators and differentiators in a regular arrangement, without the use of external coefficients. The order of the filter is increased until a stated performance is met; there is no coefficient quantization to worry about and overflows can be left undetected. The word-length of all nodes is identical as a direct consequence of the filter order and decimation ratio. The filters are flexible because any integer decimating ratio can be supported with essentially the same hardware, enabling straightforward implementation of programmable decimation ratios, a crucial feature for many systems such as software defined networks (SDN).
Although conventional CIC filters are effective, any performance improvement of the CIC filter has in the past relied on an increase in the filter order R. It would therefore be desirable and advantageous to improve the response of a filter of the aforementioned type without increasing the filter order R, to conserve or reduce area on a chip and power consumption, and more particularly to reduce the computational complexity of a filter of order R without compromising performance.